This invention relates to a technique of fabricating a semiconductor device; and, more particularly, the invention relates to a method of fabricating a semiconductor device suitable control of defective conditions which occur in the fabricating processes carried out in a semiconductor device production line.
In a semiconductor device, a conduction failure of contact holes leads to fatal defects including characteristic failures and has a significant impact on yield of the semiconductor device. Such a failure is often caused by changes in production requirements or defective conditions of manufacturing equipment and often invites a large amount of defective units.
Such defective conditions of process are controlled, in general, by a means of periodically checking for changes in pattern geometries with a critical dimension measurement SEM. However, only evaluation of pattern geometries cannot directly inspect conducting state of contact parts.
On the other hand, JP-A No. 2000-58608 etc. have disclosed A method of detecting conduction failures by using brightness of contact parts as well as pattern geometries. This method utilizes a feature of an electron microscope image. Charge-up amount of a pattern by irradiation of electron beams varies depending on the conducting states of contact parts and shows contrast between normal parts and defective parts on a secondary electron image to be detected. With such a method as this, it is possible to inspect electrical characteristics that cannot be checked by a visual check of the external view.
In recent years, wafer inspection apparatus using SEM images has also come to be utilized as has been disclosed in JP-A Nos. 1993-258703 and 2000-208085 and efficient defect inspection has become possible. This kind of apparatus utilizes repeatability of the same patterns containing devices such as cells and chips within the conductor traces and compares images of these patterns to detect defects.
As stated above, a method using SEM images has come into widespread usage as a means of detecting electrical conduction failures of contact windows. However, it requires considerably long time to obtain an SEM image with a high signal-to-noise ratio and high resolution; it takes a few hours to tens of hours to perform inspection of a whole wafer. Therefore, the in-line usage is difficult. In addition, an inspection method of performing comparison of images has a drawback in that, on the quantity occurrence of defects, images of the defects are compared with each other, making an accurate defect inspection difficult.
In addition, all of these inspection methods are intended for defect inspection, so thy cannot predict occurrence of electrical conduction failures. However, since failures caused by changes in production requirements and defective conditions of manufacturing equipment can suddenly be encountered in a large amount and on a massive scale and invite too many wafers with defects at the same time of the occurrence, it is desirable to detect changes in processes.
This invention provides A method of keeping track of failure occurrence conditions on a whole wafer of interest by using as small area subject to an inspection as possible.
This invention also provides A method of controlling changes in processes to prevent a rash of failures caused by defective conditions of manufacturing equipment.
In this invention, inspection is performed by obtaining charged particle beam images at a desired area on the surface of a wafer, calculating a typical signal amount value typifying the signal amount of charged particle beams emitted by each pattern from the obtained images, and estimating failure occurrence conditions outside the image-obtained area from the statistic of the typical signal amount value. In addition, this invention makes it easier to determine the causes of failures by providing a function for displaying the time series data of section results for each equipment which treated the wafer.
In other words, this invention, in A method of inspecting a wafer on the surface of which the same pattern is repetitively formed, comprises the steps of obtaining a charged particle beam image of a desired area of the wafer by detecting secondary charged particles emitted from the surface of the wafer with irradiation of a focused charged particle beam onto the surface of the wafer, calculating the image feature amount of each pattern within the desired area from the obtained charged particle bean images, computing the statistic of the calculated image feature amount, comparing a preset value to the computed statistic of the image feature amount, and estimating the quality of patterns that have been formed outside the desired area from the result of the comparison.
In addition, this invention, in A method of inspecting a wafer having patterns that have been repetitively formed on the surface of the wafer and have differences in geometries within a chip or interconnecting conditions with a lower layer or in both, comprises the steps of:
obtaining a charged particle beam image of a desired area of a wafer,
calculating the image feature amount of each pattern contained in the obtained charged particle beam image from the obtained charged particle beam image,
determining the statistic of the image feature amount computed for each pattern type,
comparing a threshold that has been preset in association with a pattern type to the statistic that has been computed for that pattern type, and
estimating the quality of patterns that have been formed outside the desired area from the result of the comparison.
Furthermore, this invention, in A method of inspecting a wafer on which a plurality of chips with the same pattern of traces are formed, comprises the steps of:
obtaining a charged particle beam image of a specific place on one of the plurality of chips by focusing charged particle beams onto the specific place,
estimating the failure occurrence conditions of the remaining chips on the wafer with the help of inspection data obtained from the charged particle beam image of the specific section,
determining the distribution of the estimated failure occurrence conditions of the chips on the wafer, and
outputting information of the distribution of the failure occurrence conditions on the wafer to be inspected.
This invention, in A method of manufacturing a semiconductor device, comprises the steps of:
obtaining a charged particle beam image of a preset place by irradiating a focused charged particle beam onto the preset place on a wafer that has been operated upon in given processing stages,
repeating this step for a plurality of wafers that have been operated upon in the given processing stages, and
comparing the brightness of the charged particle beam images of the specific places which have sequentially been obtained from the plurality of wafers with the preset values to control changes in process of the given processing stages.
This invention, in A method of manufacturing a semiconductor device, comprises the steps of
determining the distribution of failures over a wafer from a charged particle beam image obtained by irradiating a focused charged particle beam onto a plurality of preset sections on a wafer that has been operated upon in given processing stages, and
controlling changes in process of the given processing stages on the basis of verifications in distribution of failures from wafer to wafer.
This invention, in A method of manufacturing a semiconductor device by processing it through a plurality of processing stages, comprises the steps of:
obtaining a charged particle beam image of a preset section by irradiating a focused charged particle beam onto a preset place on a given wafer after the given wafer has been operated upon in each of the plurality of processing stages,
repeating the step for each of the plurality of processing stages, and
monitoring the brightness of the charged particle beam images obtained for each processing stage to control the plurality of processing stages.
These and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.